The eCDR-PLL, a radiation-tolerant ASIC for clock and data recovery and deterministic phase clock synthesis
نویسندگان
چکیده
منابع مشابه
The eCDR-PLL, a radiation-tolerant ASIC for clock and data recovery and deterministic phase clock synthesis
A radiation-tolerant CDR/PLL ASIC has been developed for the upcoming LHC upgrades, featuring clock Frequency Multiplication (FM) and Clock and Data Recovery (CDR), showing deterministic phase and low jitter. Two FM modes have been implemented: either generating 40, 60, 120 and 240 MHz clock outputs for GBT-FPGA applications or providing 40, 80, 160 and 320 MHz clocks for TTC and e-link applica...
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Modern communication and computer systems require rapid (Gbps), efficient and large bandwidth data transfers. Agressive scaling of digital integrated systems allow buses and communication controller circuits to be integrated with the microprocessor on the same chip. The Peripheral Component Interconnect Express (PCIe) protocol handles all communcation between the central processing unit (CPU) a...
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* This work was supported, in part, by Texas Instruments Inc., RocketChips Inc. and the R. J. Carver trust. Abstract – The Phase-Locked Loop (PLL) is a widely used block in data and clock recovery circuits. Phase detectors form a crucial part of the PLL. The requirements for phase detectors used in random data recovery are more stringent than the one used for clock recovery, especially at highs...
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Conventional PLL design techniques used to implement CMOS GHz range clock recovery circuits typically suffer from significant power supply coupled noise in large integrated systems. This noise worsens the jitter of the PLL and degrades the system Bit-ErrorRate (BER). This paper describes an analog approach which applies fully differential current steering technique throughout the whole PLL sy...
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ژورنال
عنوان ژورنال: Journal of Instrumentation
سال: 2015
ISSN: 1748-0221
DOI: 10.1088/1748-0221/10/03/c03024